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Silicon Labs /EFM32PG22C200F256IM32 /TIMER2_S /CC1_CFG

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Interpret as CC1_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OFF)MODE 0 (COIST)COIST 0 (PIN)INSEL 0 (PULSE)PRSCONF 0 (DISABLE)FILT 0 (ICFWL)ICFWL

MODE=OFF, INSEL=PIN, FILT=DISABLE, PRSCONF=PULSE

Description

No Description

Fields

MODE

CC Channel Mode

0 (OFF): Compare/Capture channel turned off

1 (INPUTCAPTURE): Input Capture

2 (OUTPUTCOMPARE): Output Compare

3 (PWM): Pulse-Width Modulation
COIST

Compare Output Initial State
INSEL

Input Selection

0 (PIN): TIMERnCCx pin is selected

1 (PRSSYNC): Synchornous PRS selected

2 (PRSASYNCLEVEL): Asynchronous Level PRS selected

3 (PRSASYNCPULSE): Asynchronous Pulse PRS selected
PRSCONF

PRS Configuration

0 (PULSE): Each CC event will generate a one EM01GRPACLK cycle high pulse

1 (LEVEL): The PRS channel will follow CC out
FILT

Digital Filter

0 (DISABLE): Digital Filter Disabled

1 (ENABLE): Digital Filter Enabled
ICFWL

Input Capture FIFO watermark level

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data